4432-T-B1 B 915【PDF 41/47 页】KIT DEV TEST EZRADIOPRO SI4432

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Si4430/31/32-B1

Rev 1.1

6. Data Handling and Packet Handler

The internal modem is designed to operate with a packet including a 010101... preamble structure. To configure the

modem to operate with packet formats without a preamble or other legacy packet structures contact customer

support.

6.1. RX and TX FIFOs

Two 64 byte FIFOs are integrated into the chip, one for RX and one for TX, as shown in Figure 17. "Register 7Fh.

FIFO Access" is used to access both FIFOs. A burst write, as described in "3.1. Serial Peripheral Interface (SPI)"

on page 18, to address 7Fh will write data to the TX FIFO. A burst read from address 7Fh will read data from the

RX FIFO.

Figure 17. FIFO Thresholds

The TX FIFO has two programmable thresholds. An interrupt event occurs when the data in the TX FIFO reaches

these thresholds. The first threshold is the FIFO almost full threshold, txafthr[5:0]. The value in this register

corresponds to the desired threshold value in number of bytes. When the data being filled into the TX FIFO crosses

this threshold limit, an interrupt to the microcontroller is generated so the chip can enter TX mode to transmit the

contents of the TX FIFO. The second threshold for TX is the FIFO almost empty threshold, txaethr[5:0]. When the

data being shifted out of the TX FIFO drops below the almost empty threshold an interrupt will be generated. If

more data is not loaded into the FIFO then the chip automatically exits the TX State after the ipksent interrupt

occurs. The chip will return to the mode selected by the remaining bits in SPI Register 07h. For example, the chip

may be placed into TX mode by setting the txon bit, but with the xton bit additionally set. For this condition, the chip

will transmit all of the contents of the FIFO and the ipksent interrupt will occur. When this interrupt event occurs, the

chip will clear the txon bit and return to READY mode, as indicated by the set state of the xton bit. If the pllon bit D1

is set when entering TX mode (i.e., SPI Register 07h = 0Ah), the chip will exit from TX mode after sending the

packet and return to TUNE mode.

However, the chip will not automatically return to STANDBY mode upon exit from the TX state, in the event the TX

packet is initiated by setting SPI Register 07h = 08h (i.e., setting only txon bit D3). The chip will instead return to

READY mode, with the crystal oscillator remaining enabled. This is intentional; the system may be configured such

that the host MCU derives its clock from the MCU_CLK output of the RFIC (through GPIO2), and this clock signal

must not be shut down without allowing the host MCU time to process any interrupt signals that may have

occurred. The host MCU must subsequently perform a WRITE to SPI Register 07h = 00h to enter STANDBY mode

and obtain minimum current consumption.

TX FIFO

RX FIFO

RX FIFO Almost Full

Threshold

TX FIFO Almost Empty

Threshold

TX FIFO Almost Full

Threshold

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